1. Field of the Invention
This invention relates generally to detector circuits for automatic test equipment, and more particularly to detector circuits for receiving differential signals from a device under test (DUT).
2. Description of Related Art
Automatic test equipment (ATE) plays a significant role in the manufacture of semiconductor devices. Manufacturers generally use automatic test systems—or “testers”—to verify the operation of semiconductor devices at the wafer and packaged device stages of the semiconductor manufacturing process. By testing semiconductor devices at these stages, manufacturers are able to reject defective devices early, eliminating costs that would otherwise be incurred by processing defective parts. Manufacturers also use ATE to grade various specifications of devices. Devices can be tested and categorized according to performance in significant areas, for example, speed. Parts can then be labeled and sold according to their tested levels of performance.
FIG. 1 is a highly simplified schematic of a conventional tester 100. The tester 100 includes a host computer 118 that runs software for controlling various tests to be performed on a DUT 122. The software prescribes signal characteristics for applying stimuli to a DUT and for sampling responses from the DUT. A pattern generator (not shown) translates the signal characteristics into timing signals. Specialized circuits called pin electronics channels (110a–110e) then convert the timing signals into actual stimuli and timing windows.
The pin electronics channels provide a signal interface between the tester and the DUT. Each pin electronics channel typically includes a driver circuit 112, a detector circuit 114, and channel overhead circuitry 116. Each channel 110a–110e has an I/O terminal, respectively 120a–120e, which can be coupled to a node of the DUT 122. The channel overhead circuitry 116 typically includes DACs (digital-to-analog converters) for establishing drive levels of the driver circuit 112 and DACs for establishing detect levels of the detector circuit 114. It may also include timing formatters for adjusting the timing of drive edges and detect windows, and memory for storing digital patterns.
Testers use detector circuits for sampling signals generated by a DUT. Traditionally, detector circuits have been for sampling single-ended signals, i.e., for determining whether a single-ended signal is in a high logic state, a low logic state, or a logic state between high and low (a “between” state). Recently, detectors have also been used for sampling differential signals. In contrast with single-ended signals, which provide one signal for conveying a digital logic state with reference to a digital ground, differential signals convey digital logic states as differences between two signals, neither of which is digital ground. An example of a differential detector is presented in U.S. Pat. No. 6,281,699, entitled, “Detector With Common Mode Comparator For Automatic Test Equipment,” which is hereby incorporated by reference in its entirety. As disclosed in that patent, a detector circuit includes a differential amplifier and a common mode amplifier. The differential amplifier produces a signal proportional to the difference between the two legs of an inputted differential signal, and the common mode amplifier produces a signal proportional to their average. The differential and common mode components of the differential signal can then be individually tested using window comparators.
Rapid advances in SerDes (Serializer/Deserializer) and SONET (Synchronous Optical Network) technologies have pushed differential signal speeds well above 1 GHz. Testing differential signals at these high speeds has posed new and difficult challenges for ATE manufacturers. In particular, it was once possible to rely upon careful fixture wiring to ensure that the delays of different legs of a differential signal were adequately matched, i.e., deskewed, with respect to each other. At data rates above 1 GHz, this is no longer the case. Even minute differences in the lengths or electrical characteristics of fixture wires or other parts of an ATE system can misalign the complementary edges of a differential signal. When these edges are misaligned, a differential amplifier within the tester that receives the differential signal produces edges that are artificially stretched in time, and a common mode amplifier produces signals having artificial spikes.
We have considered different approaches for correcting differential detector skew. For example, verniers (i.e., variable delay lines) can be positioned in series with the legs of a differential signal. The delays of the verniers can be adjusted so that the legs of the differential signal cross at precisely their 50% points. We have recognized that verniers suffer from certain drawbacks, however. For example, a vernier generally produces an output signal whose shape is different from the shape of its input signal. Changes in signal shape prevent a test system from accurately measuring certain characteristics of input signals, such as edge speeds and ringing.
What is needed is an accurate technique for deskewing differential signals received by a test system, which does not negatively impact the tester's ability to discern the analog characteristics of test signals.